TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 164

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.19
input or output. Resetting sets ports T0 to T7 to input port and output latch to “0”.
data bus pin for LCD controller (LD8 to LD15).
Port T (PT0 to PT7)
Ports T0 to T7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
In addition to functioning as general-purpose I/O port, PT0 to PT7 can also function as a
Setting in the corresponding bits of PTCR and PTFC enables the respective functions.
(on bit basis)
(on bit basis)
Output latch
LD8 to LD15
Direction
Function
PT write
control
Reset
control
PTCR write
PTFC write
PT read
S
Figure 3.7.52 Port T0 to T7
A
B
Selector
Selector
92CF26A-162
S
S
A
B
PT0 to PT7
(LD8 to LD15)
TMP92CF26A
2009-06-25