TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 165

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PT
(00A0H)
PTDR
(009BH)
PTCR
(00A2H)
PTFC
(00A3H)
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note1: A read-modify-write operation cannot be performed for the registers PTCR, PTFC.
Note2: When PT is used as LD15 to LD8, set applicable PTnC to”1”.
PT7C
PT7F
PT7D
PT7
7
7
7
0
−
0
−
7
1
−
PT6C
PT6D
PT6F
PT6
Figure 3.7.53 Register for Port T
6
6
6
0
−
1
−
6
0
−
Data from external port (Output latch register is cleared to “0”)
Input/Output buffer drive register for standby mode
Port T function register
0: Port 1: Data bus for LCDC (LD15 to LD8)
Port T control register
PT5C
PT5D
PT5F
PT5
Port T drive register
5
5
5
1
−
0
−
5
0
−
92CF26A-163
Port T register
PT4C
PT4D
0: Input 1: Output
PT4F
PT4
4
4
4
0
−
1
−
4
0
−
R/W
R/W
W
W
−
PT3C
PT3D
PT3F
PT3
3
3
3
0
−
3
1
−
0
−
PT2C
PT2D
PT2F
PT2
2
2
2
0
−
2
0
−
1
−
PT1D
PT1C
PT1F
PT1
1
1
1
0
−
1
0
−
1
−
TMP92CF26A
PT0C
PT0D
PT0F
PT0
0
0
0
0
−
0
0
−
1
−
2009-06-25