TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 166

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.7.20
input or output. Resetting sets port U0 to U7 to input port and output latch to “0”.
data bus pin for LCD controller (LD16 to LD23) and as the SDCLK input function.
communication for debug mode (EO_TRGOUT). These functions are operated when it is
started in debug mode. In this case, PU7 can not be used as LD23 function.
Port U (PU0 to PU7)
Ports U0 to U7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
In addition to functioning as general-purpose I/O port, PU0 to PU7 can also function as a
Setting in the corresponding bits of PUCR and PUFC enables the respective functions.
In addition to functioning as above function, PU7 can also function as the
LD16 to LD20, LD22,LD23
(on bit basis)
EO_TRGOUT
(on bit basis)
Output latch
Direction
Function
control
Reset
PUCR write
control
PUFC write
PU write
PU read
R
Figure 3.7.54 Port U0 to U4 , U6 , U7
A
B
Debug mode
C
Selector
Selector
S
S
92CF26A-164
A
B
PU0~PU4,PU6
PU7
(LD16 to LD20,LD22)
(LD23,EO_TRGOUT)
TMP92CF26A
2009-06-25