TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 169
TMP92xy26AXBG
Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet
1.TMP92XY26AXBG.pdf
(768 pages)
Specifications of TMP92xy26AXBG
Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
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3.7.21
Note: SIO function support function that input clock from SCLK0, basically. However, if setting to PV0 pin, this
individually for input or output. Resetting sets port V0 to V2, V6 and V7 to input port and
output latch to “0”.
output pin for SBI (SDA, SCL) and an output for SIO(SCLK0) (Note).
to output latch to “0”.
Port V (PV0 to PV4, PV6, PV7)
Ports V0 to V2, V6 and V7 are 5-bit general-purpose I/O ports. Each bit can be set
In addition to functioning as general-purpose I/O port, PV can also function as a input or
Setting in the corresponding bits of PVCR and PVFC enables the respective functions.
Ports V3 and V4 are 2-bit general-purpose output ports. Resetting clear ports V3 and V4
function supports only the output function.
Direction control
Function control
(on bit basis)
(on bit basis)
PV read
Output latch
SCLK0 output
PVFC write
PVCR write
PV write
Reset
R
Figure 3.7.57 Port V0 to V2
A
B
Selector
S
92CF26A-167
Selector
S
B
A
PV0 (SCLK0)
PV1
PV2
TMP92CF26A
2009-06-25
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