TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 171

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

PVFC
(00ABH)
PVFC2
(00A9H)
PV
(00A8H)
PVCR
(00AAH)
PVDR
(009DH)
PV2 setting
<PV7F>
<PV2F>
PV7 setting
<PV2C>
<PV7C>
0
1
0
1
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
bit Symbol
Read/Write
System
Reset State
Hot Reset
State
Function
Note: A read-modify-write operation cannot be performed for the registers PVCR, PVFC and PVFC2.
Reserved
Reserved
Input port
Input port
0
0
0: CMOS
1: Open
(Output latch register is
Refer to following table
Data from external port
PV7F2
-drain
PV7C
PV7D
PV7F
0: Input 1: Output
PV7
Output port
Output port
7
7
7
7
7
0
−
0
−
0
−
1
−
cleared to “0”)
Reserved
SCL I/O
1
1
R/W
R/W
W
W
−
0: CMOS
1: Open
PV6F2
-drain
PV6C
PV6D
PV6F
PV6
Figure 3.7.60 Register for Port V
6
6
6
0
−
6
−
6
0
−
0
−
1
PV6 setting
PV1 setting
<PV6F>
<PV1F>
Input/Output buffer drive register for standby mode
<PV1C>
<PV6C>
0
1
0
1
Port V function register 2
Port V function register
Port V control register
Port V drive register
5
5
5
5
5
92CF26A-169
Port V register
Reserved
Reserved
Input port
Input port
0
0
PV4D
PV4
4
4
4
4
4
1
−
Output port
Output port
(Output latch register is cleared to “0”)
Reserved
SDA I/O
PV3D
PV3
1
1
3
3
3
3
3
−
1
Data from external port
PV0 setting
Note: SCLK0 is only output.
PV2C
PV2F
PV2D
<PV0F>
R/W
R/W
PV2
2
2
2
2
2
−
0
−
0
−
1
−
Refer to following table
<PV0C>
0
1
0: Input 1: Output
PV1C
PV1F
PV1D
PV1
W
W
1
Reserved
0
1
1
Input port
1
1
−
0
−
1
−
0
TMP92CF26A
PV0D
PV0C
PV0F
PV0
0
0
0
0
0
−
0
−
0
Output port
1
−
2009-06-25
SCLK0
output
1