TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 172

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
TMP92CF26A
3.7.22
Port W (PW0 to PW7)
Ports W0 to W7 are 8-bit general-purpose I/O ports. Each bit can be set individually for
input or output. Resetting sets ports W0 to W7 to input port and output latch to “0”.
Setting in the corresponding bits of PWCR and PWFC enables the respective functions.
Reset
Direction
control
(on bit basis)
PWCR write
Function
control
(on bit basis)
PWFC write
PW0 to PW7
R
Output latch
PW write
S
B
Selector
PW read
A
Figure 3.7.61 Port W0 to W7
2009-06-25
92CF26A-170

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