TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 189

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(2) Memory specification
(3) Data bus width specification
Note 1: SDRAM can be associated with the CS1 or CS2 space.
Note1: The data bus width for SDRAM should be defined as 16 bits by setting BnCSH<BnBUS1:BnBUS0> to 01.
Note: If two memories with different bus widths are assigned to consecutive addresses, do not execute an
BnCSH<BnOM1:0>
BnCSH<BnBUS1:BnBUS0>
<BnBUS1> <BnBUS0>
with each address spaces. The interface signal that corresponds to the specified memory
type is generated. The memory type is specified as follows:
BnCSH<BnBUS1:BnBUS0> bits as follows:
controller to transfer operands to or from the selected address spaces while automatically
determining the data bus width. On which part of the data bus the data is actually placed
is determined by the data size, bus width and start address. The table below provides a
detailed description of the actual bus operation.
setting information of when the memory bus width is set to be 32 bits in the table.
BnOM1
Setting the BnCSH<BnOM1:BnOM0> bits specifies the memory type that is associated
The
As described above, the TMP92CF26A supports dinamic bus sizing, which allows the
The TMP92CF26A has only 16 external data bus pins. Therefore, please ignore the
instruction that accesses the addresses crossing the boundary between those memories. Otherwise, a
read/write operation might not be performed correctly.
0
0
1
1
0
0
1
1
data
BnOM0
bus
0
1
0
1
0
1
0
1
width
SRAM/ROM (Default)
can
92CF26A-187
Memory Type
(Reserved)
(Reserved)
8-bit bus mode (Default)
SDRAM
Don’t use this setting
be
16-bit bus mode
Bus Width
Reserved
specified
for
each
address
space
TMP92CF26A
2009-06-25
by
the