TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 194

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
Read
cycle
Write
cycle
A23 to A0
D15 to D0
D15 to D0
(80MHz)
R/
SDCLK
CSn
RD
SRxxB
SRWR
SRxxB
WRxx
W
TCRS:The delay from CSn to RD,SRxxB.
Note: Wait states (TWs) are inserted as specified by the BnCSL register. No TW is inserted if the number of wait state
RDTMGCR0/1<BnTCRS1:BnTCRS0>
is specified as zero.
00
01
10
11
TAC
T1
T2
TCRS
TCWS
TCWS
TCRS = 0.5 × 1/f
92CF26A-192
TCRS = 1.5 × 1/f
TCRS = 2.5 × 1/f
TCRS = 3.5 × 1/f
T3
Output
SYS
(Default)
SYS
SYS
SYS
TW
Tn-2
Input
TCWH
Output
Tn-1
TCRH
TMP92CF26A
2009-06-25
Tn
TAC

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