TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 199

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.8.4
The page mode operation to ROM is specified by PMEMCR.
D0~D15
A0~A23
(1) Operations and register settings
SDCLK
This section describes page mode access operations to ROM and the required register settings.
Note: Specify the number of wait states (n) using the control register (BnCSL) for each address space.
PMEMCR<OPWR1:OPWR0>
PMEMCR<PR1:PR0>
CS
Controlling the Page Mode Access to ROM
RD
configured for this mode of access. The page mode operation to ROM is specified by the
Page ROM Control register, PMEMCR.
to page mode.
PMEMCR<OPWR1:OPWR0> bits.
<OPWR1> <OPWR0>
PMEMCR<PR1:PR0>. When the specified page boundary is reached, the controller
terminates the page read operation. The first data of the next page is read in the normal
mode. Then, the following data is read again in page mode.
2
<PR1>
The TMP92CF26A supports page mode accesses to ROM. Only the CS2 space can be
Setting the PMEMCR<OPGE> bit to 1 sets the mode of memory access to the CS2 space
The
The page size (the number of bytes) of ROM as seen from the CPU is determined by
Figure 3.8.5 Page Mode Access Timing (when using a 8-byte page size)
0
0
1
1
0
0
1
1
number
t
CYC
t
AD3
<PR0>
t
RD3
0
1
0
1
+ 0
0
1
0
1
of
cycles
Input
Data
92CF26A-197
Number of Cycles in Page Mode
ROM Page Size
required
16 bytes (Default)
t
t
HA
AD2
2 cycles (n-2-2-2 mode) (n ≥ 3)
3 cycles (n-3-3-3 mode) (n ≥ 4)
4 cycles (n-4-4-4 mode) (n ≥ 5)
1 cycle (n-1-1-1 mode) (n ≥ 2)
64 bytes
32 bytes
8 bytes
+ 2
Input
Data
for
a
t
t
HA
AD2
read
+ 4
Input
Data
cycle
t
t
HA
AD2
is
+ 6
specified
Input
Data
TMP92CF26A
t
t
HA
HR
2009-06-25
by
the