TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 202

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.8.6
(1) Timing for the
Example: When using an externally connected NOR flash whose commands are compatible with the standard
Notes
Select) signal line, the deassertion timing of the read signal is delayed, which may lead to
an unintentional extension of a read cycle. Such an unintended read cycle extention,
which is indicated as (a) in Figure 3.8.6, may cause a problem.
cannot read the toggle bit properly and it always reads the same value from the toggle bit.
adjustment
<BnTCRH1:BnTCRH0>).
If the load capacitance of the
When the toggle bit is inverted due to this unexpected read cycle extension, the CPU
To avoid this situation, it is recommended to perform data polling or to use the timing
JEDEC commands, the toggle bit may not be read correctly. If the rising edge of the read signal in the cycle
immediately preceding the NOR flash access cycle does not occur in time, a read cycle may be extended
unintentilnally as indicated as (b) in Figure 3.8.7.
Figure 3.8.6 Read Cycle of When the Read Signal is Delayed
SDCLK
(60 MHz)
A23 to A0
CSm
CSn
RD
chip select
NOR flash
A23 to A0
Toggle bit
(60 MHz)
function
Figure 3.8.7 NOR Flash Toggle Bit Read Cycle
SDCLK
CS
RD
and
Memory access
RD
for
signals
92CF26A-200
the
RD
(Read) signal line is greater than that of the
rising
(b)
Toggle bit RD cycle
edge
of
(a)
the
RD
signal
TMP92CF26A
(RDTMGCRn
2009-06-25
CS
(Chip