TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 209

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.9.2
data (program, read data, write data, LCD-display data, source data for DMA channels of
odd/even number, destination-data for DMA channels of odd/even number) for each of
three-LOCAL areas (LOCAL-X through LOCAL-Z). These registers allow for easy data access.
The TMP92CF26A MMU has 24 registers. These registers are used for storing eight types of
Note1: When programming the bank registers, the bank area that is overlapping with the COMMON area must not be
Note2: In the LOCAL area, changing Program bank number (LOCALPX, Y or Z) is disabled. Program bank setting of
Note3: After setting values specifying the data bank number into bank registers for the read, write, DMA and LCD
Note4: When the LOCAL-Z area is used, pin P82 should be assigned as the chip select signal
(*1) This setting is not required if the COMMON-Z area is not used to store write data.
(*2) This setting is not required if the COMMON-Z area is not used to store display data for LCD.
enable/disable the specified bank. Then, configure the external pins to be used and also the
Memory Controller. Then, when the CPU or LCDC accesses a logical address in the LOCAL
area, the MMU translates the logical address to the corresponding physical address
according to the programmed bank configuration. The physical address is then placed on
the external address bus pin, which enables external memory accesses. Thus, even when a
program accesses the same logical address, its physical address changes depending on the
bank specified by the program bank register. This enables memory accesses to the different
memory banks.
Control registers
(How to use the control registers)
First, load the control registers for each LOCAL area with the desired bank number and
specified ( because addresses of those areas are converted to the same physical addresses).
each LOCAL area must change in COMMON area. (But bank setting of data-Read, data-Write and
LCDC-display data can change also in LOCAL area.)
display data (LOCALRn, LOCALWn or LOCALLn, LOCALEDn, LOCALSn, LOCALODn; the symbol “n”
indicates X, Y or Z), the specified bank requires a certain setup time to be enabled. Thus, the bank cannot be
accessed by an instruction immediately following the register setting instructions. In this case, insert a dummy
instruction which accesses SFR or another memory area as shown in the following example.
After reset, pin P82 should be properly configured following the procedure below.
CSZA
(Example)
works as the chip select signal for the bank 0 through the bank 15, and also for the COMMON-Z area.
ld
ldw
ldw
ldw
ldw
ldw
ldw
ldw
ld
ld
(localpz), 8000h
(localrz), 8000h
(localwz), 8000h
(locallz), 8000h
(P8FC),
(P8FC2),
xix, 200000h
(localrx), 8001h
wa, (localrx)
wa, (xix)
− − − − − 0 − − B
− − − − − 1 − − B
92CF26A-207
;
; Specify the read-data bank number
; ← Inserted dummy instruction which accesses SFR
; instruction which reads bank 1 of the LOCAL-X area.
; Enable the banks in LOCAL-Z for program
; Enable the banks in LOCAL-Z for read data
; Enable the banks in LOCAL-Z for write data (*1)
; Enable the banks in LOCAL-Z for LCD display memory
; Assign P82 as the
;
(*2)
CSZA
output
CSZA
TMP92CF26A
. In this case,
2009-06-25