TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 220

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

LOCALODY
(08BAH)
(08BBH)
LOCALODZ
(08BCH)
(08BDH)
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
Bit Symbol
Read/Write
Reset State
Function
BANK for
LOCAL-Y
0: Disable
Bank for
LOCAL-Z
0: Disable
1: Enable
1: Enable
LYE
R/W
R/W
LZE
15
15
Z7
7
7
0
0
0
(Since bank 3 is overlapping with the COMMON area, this filed must not be specified as 3.)
LOCAL-Y Register for the O-group DMA Destination
LOCAL-Z Register for the O-group DMA Destination
14
14
Z6
6
6
0
Settings of the Z8 through Z0 bits and their corresponding chip select signals
000000000 to 001111111 CSZA
010000000 to 011111111 CSZB
(Since bank 3 is overlapping with the COMMON area, this filed must not be
Specify the bank number for the LOCAL-Z area
13
92CF26A-218
13
Z5
Y5
5
5
0
0
Specify the bank number for the LOCAL-Z area
Specify the bank number for the LOCAL-Y area
12
12
Y4
Z4
4
4
0
0
R/W
11
Y3
11
Z3
3
3
specified as 3.)
0
0
100000000 to 101111111 CSZC
110000000 to 111111111 CSZD
R/W
10
10
Y2
Z2
2
2
0
0
Y1
Z1
1
9
1
9
0
0
TMP92CF26A
2009-06-25
R/W
Y0
Z0
Z8
0
8
0
8
0
0
0