TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 221

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.9.3
No.
(a)
(b)
(c)
(d)
(e)
Address
C00000H
C000xxH
C000yyH
Logical
•
•
•
•
The conditions listed in this table apply the following programming examples.
(a) Main Routine (COMMON-Z)
Note: This example assumes that the subroutine program is already written into SRAM.
Display-RAM
Programming example
Subroutine
Character-
Used as
The instructions No.2 through No.8 configure external pins and the Memory Controller.
The instruction No.9 specifies the stack pointer value. The stack pointer is herein
The instruction No.10 configures the setting used for a subroutine call instruction of
The instruction No.12 calls a subroutine. When the CPU generates the address 400000H,
specified to point to the memory location in on-chip RAM.
No.12.
the MMU translates it to the physical address 000000H, which is then placed onto the
external address bus: A23 to A0. Since the logical address is within the address range of
the CS1 space,
the program execution of the CPU can be branched to the subroutine.
Routine
Stack-
ROM
RAM
Main
LCD
Physical
Address
<-(Same)
<-
<-
(16 MB, 1 pcs)
(16 MB, 1 pcs)
Instruction
On-chip-RAM
NOR-Flash
Memory
(144KB)
SRAM
No.
5.1
5.2
CS
10
11
12
13
14
15
1
2
3
4
5
6
7
9
1
for SRAM is asserted at the same time. By using these instructions,
org
ldw
ldw
ldw
ldw
ldw
ldw
ld
ld
ld
ldw
call
:
:
:
:
(32 bit, 2-1-1-1clk)
92CF26A-219
(mamr2),80FFH
(b2csl), C222H
(mamr1),40FFH
(b1csl), 8111H
(localpy),8000H
(p8fc), 02H
(p8fc2), 04H
xsp,48000H
C00000H
(localpz),8000H
(localrz),8000H
400000H
1 wait state
0 wait state
Setting
CSZA ,
32 bit,
16 bit,
Instruction
CS ,
−
1
MMU area
COMMON-Z
LOCAL-Y
LOCAL-Y
Bank 0 in
LOCAL-Z
Bank 0 in
Bank 1 in
Bank 2 in
LOCAL-Y
;
; CS2 800000-FFFFFF/8MB
; CS2 32-bit ROM, 1 wait state
; CS1 400000-7FFFFF/4MB
; CS1 16-bit RAM, 0 wait state
; Enable LOCAL-Z bank for program
; Enable LOCAL-Z bank for read-data
;
;
; Stack Pointer = 48000H
; Bank 0 in LOCAL-Y is configured as the
;
; Call a subroutine
;
;
;
program bank for subroutines
800000H to
400000H to
address
BFFFFFH
5FFFFFH
Logical
Comment
C00000H to
FFFFFFH
002000H to
049FFFH
TMP92CF26A
000000H to
000000H to
200000H to
Physical
address
3FFFFFH
1FFFFFH
3FFFFFH
2009-06-25