TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 223

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.10 SDRAM Controller (SDRAMC)
can be used as data memory, program memory, or display memory.
(1) Supported SDRAM
(2) Supported initialization sequence commands
(3) Access mode
(4) Access cycles
(5) Auto generation of refresh cycles
The TMP92CF26A incorporates an SDRAM controller (SDRAMC) for accessing SDRAM that
The SDRAMC has the following features:
•
•
•
CAS latency (clock)
Note: The SDRAM address area is determined by the CS1 or CS2 setting of the memory controller. However, the
Data rate type
Memory capacity
Number of banks
Data bus width
Read burst length
Write mode
Precharge All command
Eight Auto Refresh commands
Mode Register Set command
CPU access cycles
HDMA access cycles
LCDC access cycles
Addressing mode
Auto Refresh is performed while the SDRAM is not being accessed.
The Auto Refresh interval is programmable.
The Self Refresh function is also supported.
Burst length
Write mode
Read cycle
Write cycle
Data size
Read cycle
Write cycle
Data size
Read cycle
Data size
number of bus cycle states is controlled by the SDRAMC.
: 1 word, 4-3-3-3 states (minimum)
: Single, 3-2-2-2 states (minimum)
: 1 byte / 1 word / 1 long-word
: 1 word, 4-3-3-3 states / full page, 4-1-1-1 states (minimum)
: Single, 3-2-2-2 states (minimum) / burst, 2-1-1-1 states (minimum)
: 1 byte / 1 word / 1 long-word
: Full page, 4-1-1-1 states (minimum)
: 1 word
: SDR (single data rate) type only
: 16 / 64 / 128 / 256 / 512 Mbits
: 2 banks / 4 banks
: 16 bits
: 1 word / full page
: Single mode / Burst mode
CPU Cycle
Sequential
1 word
Single
2
92CF26A-221
1 word or full page selectable
Single or burst selectable
HDMA Cycle
Sequential
2
LCDC Cycle
Sequential
Full page
2
TMP92CF26A
2009-06-25