TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 224

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SDACR
(0250H)
SDCISR
(0251H)
SDRCR
(0252H)
3.10.1
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
The SDRAMC has the following control registers.
Control Registers
Read data
shift
function
0: Disable
1: Enable
Always
write “0”
SRDS
R/W
7
7
7
1
−
0
TMRD
0: 1 CLK
1: 2 CLK
Always
write “0”
STMRD
SDRAM Command Interval Setting Register
6
1
6
6
−
0
SDRAM Refresh Control Register
SDRAM Access Control Register
TWR
0: 1 CLK
1: 2 CLK
Address multiplex
type
00: Type A (A9- )
01: Type B (A10- )
10: Type C (A11- )
11: Reserved
SMUXW1 SMUXW0
STWR
5
1
R/W
5
5
0
92CF26A-222
TRP
0: 1 CLK
1: 2 CLK
Self
Refresh
auto exit
function
0:Disable
1:Enable
STRP
SSAE
4
1
4
0
4
1
TRCD
0: 1 CLK
1: 2 CLK
Read/Write
commands
0: Without
auto
precharge
1: With auto
precharge
Refresh interval
000: 47 states
001: 78 states
010: 156 states
011: 312 states
STRCD
R/W
SRS2
SPRE
3
1
3
0
3
0
TRC
000: 1 CLK
001: 2 CLK
010: 3 CLK
011: 4 CLK
STRC2
SRS1
2
1
R/W
100: 468 states
101: 624 states
110: 936 states
111: 1248 states
2
0
2
STRC1
SRS0
1
0
1
100: 5 CLK
101: 6 CLK
110: 7 CLK
111: 8 CLK
1
0
SDRAM
controller
0: Disable
1: Enable
Auto
Refresh
0:Disable
1:Enable
STRC0
TMP92CF26A
SMAC
R/W
0
SRC
0
0
0
0
0
2009-06-25