TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 232

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Internal system clock
Internal dat bus
Internal system
Internal data bus
COMMAND
COMMAND
(4) Read data shift function
D15-D0
SDCLK
A15-A0
D15-D0
SDCLK
A15-A0
clock
SDRAM, the read data can be latched in a port circuit so that the CPU can read the data in the
next state. When this read data shift function is used, the read cycle requires additional one
state. The write cycle is not affected. The timing waveforms for various cases are shown below.
If the AC specifications of the SDRAM cannot be satisfied when data is read from the
(a) 1-word read, the read data shift function disabled (SDACR<SRCS> = “0”)
(b) 1-word read, the read data shift function enabled (SDACR<SRDS> = “1”,
NOP
<SRDSCK>= “0”)
NOP
Row Address
Row Address
ACTIVE
ACTIVE
READ
READ
ColumnAddress
92CF26A-230
External data latch
ColumnAddress
NOP
NOP
DIN1
DIN1
CPU data read
NOP
NOP
DIN1
Row Address
DIN1
CPU data read
ACTIVE
NOP
Row Address
ACTIVE
READ
Address
Column
TMP92CF26A
2009-06-25