TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 235

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SDLUDQM
SDLLDQM
SDCAS
SDRAS
SDCKE
SDCLK
SDWE
SDCS
(b) Self Refresh
Note 1: When standby mode is released by a system reset, the I/O registers are initialized and the Self Refresh state
Note 2: The SDRAM cannot be accessed while it is in the Self Refresh state.
Note 3: To execute the HALT instruction after the Self Refresh Entry command, insert at least 10 bytes of NOP or
Figure 3.10.7 shows the Self Refresh cycle timing. Before entering Self-refresh mode, issue
the all Bank Pre-charge Command. Once Self Refresh is started, the SDRAM is refreshed
internally without the need to issue the Auto Refresh command.
Setting Example
The Self Refresh Entry command is issued by setting SDCMM<SCMM2:0> to “101”.
is exited. Note that the Auto Refresh function is also disabled at this time.
other instructions between the instruction to set SDCMM<SCMM2:0> to “101” and the HALT instruction.
org
ld
ld
dl
dl
dl
halt
dl
ld
dl
Self Refresh Entry
0x2000
(sdcmm),0x02
(sdcmm),0x05
0,0
0,0
0,0
0
(sdcmm),0x06
0
Figure 3.10.7 Self Refresh Cycle Timing
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;
;
;
;
;
;
;
;
;
;
;
92CF26A-233
Internal RAM
All Bank Precharge Command
Self Refresh Entry Command
Reduce power consumption
(like SDCLK stop)
Self Refresh Exit Command
Self Refresh Exit
Auto Refresh Mode
TMP92CF26A
2009-06-25
Set