TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 244

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
D15 ∼ D0
NDRE
NDWE
NDR/B
NDCE
NDALE
NDCLE
NDWE
D15 ∼ D0
CS
RD
SRWR
NDCLE
NDALE
NDCE
NDRE
NDR/B
A23 ∼ A0
A23∼A0
CS
SRWR
f
RD
SYS
2
f
2
SYS
the NAND Flash are performed through the ND0FDTR register. The actual write operation
completes not when the ND0FDTR register is written to but when the data is written to the
external NAND Flash. Likewise, the actual read operation completes not when the
ND0FDTR register is read but when the data is read from the external NAND Flash.
the CPU operating speed (f
the electrical characteristics.)
NDFMCR0<SPLW1:0>=2 and NDFMCR0<SPHW1:0>=2. (In write cycles, the data drive
time also becomes longer.)
The
At this time, the Low and High widths of
The following shows an example of accessing the NAND Flash in 6 clocks by setting
Program Memory Read (1 wait)
Program Memory Read (1wait)
NDRE
and
FF1234H
Figure3.11.3 Read/Write Access to NAND Flash
FF1234H
IN (Program)
IN (Program)
NDWE
signals are explained next. Write and read operations to and from
SYS
) and the access time of the NAND Flash. (For details, refer to
92CF26A-242
NAND Flash Write
NAND Flash Read
001FF0H
001FF0H
OUT (NAND Flash)
NDRE
2clk
2clk
IN (NAND Flash)
and
2clk
NDWE
2clk
can be adjusted according to
Program Memory Read (1 wait)
Program Memory Read (1 wait)
FF1238H
FF1238H
IN (Program)
IN (Program)
TMP92CF26A
2009-06-25

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