TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 247

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.11.4.2 Error Correction Methods
1) The calculated ECC and the ECC in the redundant area are rearranged, respectively,
2) The two rearranged ECCs are XORed.
3) If the XOR result is 0 indicating an ECC match, the error correction process ends
4) If the XOR result contains only one ON bit, it is determined that a single-bit error
5) If each pair of bits 0 to 21 of the XOR result is either 01B or 10B, it is determined that
6) The line and bit positions of the error are detected using the line parity and column
Hamming ECC
so that the lower 2 bytes represent line parity (LPR15:0) and the upper 1 byte (of which
the upper 6 bits are valid) represents column parity (CPR7:2).
normally (no error). If the XOR result is other than 0, it is checked whether or not the
error data can be corrected.
exists in the ECC data itself and the error correction process terminates here (error not
correctable).
the error data is correctable and error correction is performed accordingly. If the XOR
result contains either 00B or 11B, it is determined that the error data is not correctable
and the error correction process terminates here.
parity of the XOR result, respectively. The error bit thus detected is then inverted. This
completes the error correction process.
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at address 212.
Example: When the XOR result is 1001101010011001011010
Convert two bytes of line parity into one byte (10→1, 01→0).
Convert six bits of column parity into three bits (10→1, 01→0).
Line parity:
Column parity:
Based on the above, error correction is performed by inverting the data in bit 5
of valid data. The error correction process must be performed in units of 256
bytes (22 bits of ECC). The following explains how to implement error
correction on 256 bytes of valid data using 22 bits of ECC.
the error correction process must be repeated several times to cover the entire
page.
The ECC generator generates 44 bits of ECC for a page containing 512 bytes
If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes),
Binary
10 01 10 00
10 10 01 10
01 01 10 10
An Example of Correctable
92CF26A-245
10 10 01 10 01 01 10 10
10 01 10
XOR Result
1 1 0 1 0 0 1 1 = D3H
1 0 1 = 5
Column parity
Line parity
An Example of Uncorrectable
10 11 10 00
10 10 01 10
01 01 10 10
XOR Result
Column parity
Line parity
*Error at D3/FF H
*Error in bit 5
TMP92CF26A
2009-06-25