TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 248

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: If the error address (after converted) is in the range of 000H to 007H, it indicates that an error bit exists in
1) If the error address indicated by the NDRSCAn register is in the range of 000H to
2) If the error address indicated by the NDRSCAn register is in the range of 008H to
Reed-Solomon ECC
redundant area (ECC). In this case, no error correction is needed. If the number of error bits is not more than
4 symbols, Reed-Solomon codes calculate each error bit precisely even if it is the redundant area (ECC).
007H, this error exists in the ECC area and no correction is needed in this case.
(It is not able to correct the error in the ECC area. However, if the error exists in the
ECC area, only 4symbol (include the error in the ECC area) can correct the error to this
LSI. Please be careful.)
20DH, the actual error address is obtained by subtracting this address from 20 DH.
(If the valid data is processed as 512 byte, the actual error address is obtained by
subtracting this address from 207H when the error address in the range of 008H to
207H.)
Example 1:
Example 2:
•
•
needed.
error correction process inverts the data in bits 7 and 0 at address 18AH.
083H from 207H. Thus, the error correction process inverts the data in bits 7 and
0 at address 184H.)
NDRSCAn = 005H, NDRSCDn = 04H = 00000100B
As the error address (005H) is in the range of 000H to 007H, no correction is
(Although an error exists in bit 2, no correction is needed.)
NDRSCAn = 083H, NDRSCDn = 81H = 10000001B
The actual error address is obtained by subtracting 083H from 20DH. Thus, the
(If the valid data is 512 byte, the actual error address is obtained by subtracting
If the NAND Flash to be used has a large-capacity page size (e.g. 2048 bytes),
the error correction process must be repeated several times to cover the entire
page.
performed properly, the NDFC only needs to refer to the error address and
error bit. However, it may be necessary to convert the error address, as
explained below.
The ECC generator generates 80 bits of ECC for up to 518 bytes of valid data.
Basically no calculation is needed for error correction. If error detection is
92CF26A-246
TMP92CF26A
2009-06-25