TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 249

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

NDFMCR0
(08C0H)
(08C1H)
A
read-modify-
write
operation
cannot be
performed
A
read-modify
-write
operation
cannot be
performed
3.11.5
NDCLE pin
NDALE pin
NDR/B pin
<BUSY> flag
NDWE pin
(a) <ECCRST >
(b) <BUSY>
bit Symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
ECC generator. When NDFMCR1<ECCS>=“1”, setting this bit to “1” clears the
Reed-Solomon ECC. Note that this bit is ineffective when NDFMCR0<ECCE>=“0”. Before
writing to this bit, ensure that NDFMCR0<ECCE>=“1”.
when the NAND Flash is “busy” and to “0” when it is “ready”.
state is reflected on the <BUSY> flag after some delay. It is therefore necessary to inert a
delay time by software (e.g. ten NOP instructions) before checking this flag.
Description of Registers
This bit is used to check the state of the NAND Flash memory (NDR/B pin). It is set to “1”
Since the NDFC incorporates a noise filter of several states, a change in the NDR/B pin
The <ECCRST> bit is used for both Hamming and Reed-Solomon codes.
When NDFMCR1<ECCS>=“0”, setting this bit to “1” clears the Hamming ECC in the
The <BUSY> bit is used for both Hamming and Reed-Solomon codes.
Read
command
WE
enable
0: Disable
1: Enable
Strobe pulse width
(Low width of NDRE ,
Inserted width
NDWE )
= (fSYS) × (set value)
SPLW1
WE
15
Figure3.11.5 NAND Flash Mode Control 0 Register
7
0
0
Address input
ALE
control
0: “L” out
1: “H” out
SPLW0
ALE
NAND Flash Control 0 Register
14
6
0
0
CLE
control
0: “L” out
1: “H” out
Strobe pulse width
(High width of NDRE ,
Inserted width
NDWE )
= (fSYS) × (set value)
92CF26A-247
SPHW1
CLE
13
5
0
0
Delay
time
R/W
R/W
control
0: “H” out
1: “L” out
CE
SPHW0
CE0
0
12
4
0
0
control
0: “H” out
1: “L” out
Reed-
Solomon
ECC
latch
0: Disable
1: Enable
Sensing <BUSY> flag
CE
RSECCL
CE1
1
11
3
0
0
ECC
circuit
control
0: Disable
1: Enable
Reed-
Solomon
operation
0: Encode
(Write)
1: Decode
(Read)
RSEDN
ECCE
10
2
0
0
NAND
Flash
state
1: Busy
0: Ready
Reed-
Solomon
error
calculation
start
0: −
1: Start
*Always
read as
“0”.
RSESTA
BUSY
W
1
R
9
0
0
TMP92CF26A
2009-06-25
ECC
reset
control
0: −
1: Reset
*Always
read as
“0”.
Reed-
Solomon
ECC
generator
write
control
0: Disable
1: Enable
RSECGW
ECCRST
R/W
W
0
8
0
0