TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 250

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(c) <ECCE>
(d) <CE1:0>, <CLE>, <ALE>
(e) <WE>
(f)
(g) <RSESTA>
(h) <RSEDN>
Note 1: Valid data and ECC cannot be read continuously by DMA transfer. After valid data has been read, DMA
Note 2: Immediately after ECC is read from the NAND Flash, the NAND Flash access operation or error bit
generator (to set <ECCRST> to “1”), the ECC generator must be enabled (<ECCE> = “1”).
codes to control the pins of the NAND Flash memory.
write operations.
this bit should be set to “0”.
valid data or ECC is to be read. This control is implemented by software using this bit.
the redundant area in the NAND Flash, set <RSECGW> to “1”.
generated from the ECC for written data and the ECC for read data. Setting <RSESTA> to
“1” starts this calculation.
bit should be set to “0”.
read from the NDECCRDn register is written to the redundant area in the NAND Flash.
For a read operation, this bit should be set to “1” (decode). In this case, valid data is read
from the NAND Flash and the ECC written in the redundant area is also read to generate
an intermediate code for calculating the error address and error bit position.
The <RSEDN> bit is used only for Reed-Solomon codes. When using Hamming codes, this
For a write operation, this bit should be set to “0” (encode) to generate ECC. The ECC
The <ECCE> bit is used for both Hamming and Reed-Solomon codes.
This bit is used to enable or disable the ECC generator. To reset the ECC in the ECC
The <CE1:0>, <CLE>, and <ALE> bits are used for both Hamming and Reed-Solomon
The <WE> bit is used for both Hamming and Reed-Solomon codes to enable or disable
The <RSECGW> bit is used only for Reed-Solomon codes. When Hamming codes are used,
Since valid data and ECC are processed differently, the NDFC needs to know whether
To read valid data from the NAND Flash, set <RSECGW> to “0”. To read ECC written in
The <RSESTA> bit is used only for Reed-Solomon codes.
The error address and error bit position are calculated using an intermediate code
<RSECGW>
transfer should be stopped once to change the <RSECGW> bit from “0” to “1” before ECC can be read.
calculation cannot be performed for a duration of 20 system clocks (f
instructions or the like.
92CF26A-248
SYS
). It is necessary to insert 20 NOP
TMP92CF26A
2009-06-25