TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 276

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: The same memory address is allocated to the timer register and the register buffer 0. When <TA0RDE> = “0”,
the same value is written to the register buffer 0 and the timer register; when <TA0RDE> = “1”, only the register
buffer 0 is written to.
(3)
Timer registers 0 (TA0REG)
value set in the timer register TA0REG or TA1REG matches the value in the
corresponding up counter, the comparator match detect signal goes active. If the
value set in the timer register is 00H, the signal goes active when the up counter
overflows.
double buffer structure is enabled or disabled. It is disabled if <TA0RDE> = “0” and
enabled if <TA0RDE> = “1”.
the timer register when a 2
PPG cycle in PPG mode. Hence the double buffer cannot be used in timer mode.
overflow in PWM mode or frequency agreement in PPG mode.)
double buffer, write data to the timer register, set <TA0RDE> to “1”, and write the
following data to the register buffer. Figure 3.12.5 shows the configuration of
TA0REG.
Timer registers (TA0REG and TA1REG)
These are 8-bit registers, which can be used to set a time interval. When the
TA0REG has a double buffer structure, making a pair with the register buffer.
The setting of the bit TA01RUN<TA0RDE> determines whether TA0REG’s
When the double buffer is enabled, data is transferred from the register buffer to
(When using the double buffer, method of renewing timer register is only
A reset initializes <TA0RDE> to “0”, disabling the double buffer. To use the
Register buffer 0
Internal data bus
Figure 3.12.5 Configuration of timer register (TA0REG)
Shift trigger
Write
92CF26A-274
n
TA01RUN<TA0RDE>
overflow occurs in PWM mode, or at the start of the
Selector
S
B
A
Matching detection PPG cycle
2
Write to TA0REG
n
overflow of PWM
TMP92CF26A
2009-06-25