TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 287

no-image

TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
TA7FFCR
(111DH)
A read-
modify-write
operation
cannot be
performed
Bit symbol
Read/Write
Reset State
Function
Note: The values of bits 4 to 6 of TA7FFCR are “1” when read.
Inversion signal for timer flip-flop 7 (TA7FF)
(Don’t care except in 8-bit timer mode)
Control of TA7FF
Inversion of TA7FF
<TA7FFC1:0>
7
TA7FFIS
TA7FFIE
6
TMRA7 Flip-Flop Control Register
Figure 3.12.15 Register for TMRA
00
01
10
11
5
0
1
0
1
92CF26A-285
Inversion by TMRA6
Inversion by TMRA7
Disabled
Enabled
Inverts the value of TA7FF (Software inversion)
Sets TA7FF to “1”
Clears TA7FF to “0”
Don’t care
4
00: Invert TA7FF
01: Set TA7FF
10: Clear TA7FF
11: Don’t care
TA7FFC1
3
1
R/W
TA7FFC0
2
1
TA7FF
control for
inversion
0: Disable
1: Enable
TA7FFIE
1
0
R/W
TA7FF
inversion
select
0: TMRA6
1: TMRA7
TA7FFIS
TMP92CF26A
0
0
2009-06-25

Related parts for TMP92xy26AXBG