TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 291

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
Example: To generate an INTTA1 interrupt every 0.13 s at f
(2) 16 bit timer mode
Comparator output
(TMRA0 match)
TMRA0 up counter
(when TA0REG = 5)
TMRA1 up counter
(when TA1REG = 2)
TMRA1 match output
TA1REG as follows:
To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together,
set TA01MOD<TA01M1:0> to 01.
TMRA1, regardless of the value set in TA01MOD<TA01CLK1:0>. Table 3.12.2shows
the relationship between the timer (Interrupt) cycle and the input clock selection.
following value in the registers: 0.13 s ÷ 2.6 μs = 50000 = C350H; e.g. set TA1REG to
C3H and TA0REG to 50H.
c.
Pairing the two 8-bit timers TMRA0 and TMRA1 configures a 16-bit interval timer.
In 16-bit timer mode, the overflow output from TMRA0 is used as the input clock for
If φT16 (2.6 μs at f
input clock to TMRA1.
Making TMRA1 count up on the match signal from the TMRA0 comparator
Select 8-bit timer mode and set the comparator output from TMRA0 to be the
Figure 3.12.18 TMRA1 Count Up on Signal from TMRA0
* Clock state
SYS
1
Clcok gear :
Prescaler of clock gear : 1/2
= 50 MHz) is used as the input clock for counting, set the
92CF26A-289
2
3
1
4
5
SYS
1/1
1
= 50 MHz, set the timer registers TA0REG and
2
3
2
4
5
1
TMP92CF26A
2
1
2009-06-25
3

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