TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 30

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: PLL1 operates as well.
<PLL0>
PLL output: f
Lockup timer
<LUPFG>
System clock f
(Example-2) PLL0-stopping
<FCSEL>
The following is an example of settings for PLL0-starting and PLL0 stopping.
(Example-1) PLL0-starting
PLLCR0
PLLCR1
LUP:
PLLCR0
PLLCR1
X: Don't care
X: Don't care
PLL0 output: f
System clock f
<FCSEL>
<PLL0>
PLL
EQU
EQU
LD
BIT
JR
LD
SYS
EQU
EQU
LD
LD
PLL
SYS
10E8H
10E9H
(PLLCR1),1XXXXXXXXB
5,(PLLCR0)
Z,LUP
(PLLCR0), X1XXXXXXB
10E8H
10E9H
(PLLCR0),X0XXXXXXB
(PLLCR1),0XXXXXXXB
Changes from 60MHz to 10 MHz.
Starts PLL0 operation and
Starts lock-up.
92CF26A-28
Counts up by f
;
;
OSCH
;
;
;
;
During lock-up
Changes fc from 60 MHz to10 MHz.
Stop PLL
Enables PLL0 operation and starts lock up.
Detects end of lock-up
Changes fc from 10 MHz to 60 MHz.
Stops PLL0 operation .
Ends of lock-up
Changes from 10MHz to 60MHz.
After lock-up
TMP92CF26A
2009-06-25