TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 304

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(4) Capture registers (TB0CP0H/L, TB0CP1H/L)
(5) Capture input and external interrupt control
The capture registers are read-only registers and thus cannot be written to.
2-byte data load instruction or two 1-byte data load instructions. The least significant
byte is read first, followed by the most significant byte.
should be read first, followed by the 8 bits.)
TB0CP0H/L and TB0CP1H/L, and generates external interrupt.The latch timing of
capture register and selection of edge for external interrupt is controlled by
TB0MOD<TB0CPM1:0>.
Whenever 0 is written to TB0MOD<TB0CP0I>, the current value in the up counter
(UC10) is loaded into capture register TB0CP0H/L. It is necessary to keep the
prescaler in RUN mode (i.e., TB0RUN<TB0PRUN> must be held at a value of 1).
TMRB0
TMRB1
These 16-bit registers are used to latch the values in the up counter (UC10).
All 16 bits of data in the capture registers should be read. For example, using a
(during capture is read, capture operation is prohibited. In that case, the lower 8 bits
The addresses of the capture registers are as follows;
This circuit controls the timing to latch the value of the up-counter UC10 into
The value in the up-counter (UC10) can be loaded into a capture register by software.
Upper 8 bits
Upper 8 bits
(TB0CP0H)
(TB1CP0H)
118DH
119DH
TB0CP0H/L
TB1CP0H/L
Lower 8 bits
Lower 8 bits
(TB0CP0L)
(TB1CP0L)
118CH
119CH
92CF26A-302
Upper 8 bits
Upper 8 bits
(TB0CP1H)
(TB1CP1H)
118FH
119FH
TB0CP1H/L
TB1CP1H/L
Lower 8 bits
Lower 8 bits
(TB0CP1L)
(TB1CP1L)
118EH
119EH
TMP92CF26A
2009-06-25