TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 305

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: If an inversion by the match-detect signal and a setting change via the TB0FFCR register occurs
(6) Comparators (CP10, CP11)
(7) Timer flip-flops (TB0FF0)
simultaneously, the resultant operation varies depending on the situation, as shown below.
UC10 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect
a match. If a match is detected, the comparator generates an interrupt (INTTB00 or
INTTB01 respectively).
the latch signals to the capture registers. Inversion can be enabled and disabled for
each element using TB0FFCR<TB1C1T1, TB0C0T1, TB0E1T1, TB0E0T1>.
<TB0FF0C1:0>, TB0FF0 will be inverted. If “01” is written to the capture registers, the
value of TB0FF0 will be set to “1”. If “10” is written to the capture registers, the value
of TB0FF0 will be set to “0”.
simultaneously, two case (it is inverted and it is not inverted) are occurred. Therefore,
if changing inversion control (inversion enable/disable), stop timer operation
beforehand.
shared with PP6) and TB0OUT1 (which is shared with PP7). Timer output should be
specified using the port P function register.
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CP10 and CP11 are 16-bit comparators which compare the value in the up counter
These flip-flops are inverted by the match detect signals from the comparators and
After a reset the value of TB0FF0 is undefined. If “00” is written to TB0FFCR
If an inversion by match-detect signal and inversion disable setting occur
The values of TB0FF0 can be output via the timer output pins TB0OUT0 (which is
the flip-flop will be inverted only once.
occur simultaneously, the flip-flop will be set to 1.
register occur simultanerously, the flip-flop will be cleared to 0.
If an inversion by the match-detect signal and an inversion via the register occur simultaneously,
If an inversion by the match-detect siganl and an attempt to set the flip-flop to 1 via the register
If an inversion by the match-detect signal and an attmept to cleare the flip-flop to 0 via the
92CF26A-303
TMP92CF26A
2009-06-25