TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 306

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TMP92xy26AXBG

Manufacturer Part Number
TMP92xy26AXBG
Description
Manufacturer
Toshiba
Datasheet

Specifications of TMP92xy26AXBG

Package
FPGA228
Rom Types(m=mask,p=otp, F=flash,e=eeprom)
Romless
Rom Combinations
Romless
Ram Combinations
144/288
Architecture
32-bit CISC
Usb/spi Channels
1/1
Uart/sio Channels
2
I2c/sio Bus Channels
1
(s)dram Controller
1
Adc 10-bit Channel
6
Da Converter
-
Timer 8-bit Channel
8
Timer 16-bit Channel
2
Pwm 8-bit Channels
-
Pwm 16-bit Channels
-
Cs/wait Controller
4
Dual Clock
Y
Number Of I/o Ports
136
Power Supply Voltage(v)
3.0 to 3.6
TB0RUN
(1180H)
TB1RUN
(1190H)
3.13.3
Bit symbol
Read/Write
Reset State
Function
Bit symbol
Read/Write
Reset State
Function
Note: 1, 4 and 5 of TB0RUN are read as “1” values.
Note: 1, 4 and 5 of TB1RUN are read as “1” values.
SFR
Double
buffer
0: disable
1: enable
Double
buffer
0: disable
1: enable
Count operation
Count operation
TB0RDE
TB1RDE
<TB0PRUN>, <TB0RUN>
<TB1PRUN>, <TB1RUN>
R/W
R/W
7
7
0
0
Always write
“0”
Always write
“0”
R/W
R/W
6
6
0
0
Figure 3.13.3 Register for TMRB
TMRB0 RUN Register
TMRB1 RUN Register
92CF26A-304
5
5
0
1
0
1
Stop and clear
Count up
Stop and clear
Count up
4
4
In IDLE2
mode
0: Stop
1: Operate
In IDLE2
mode
0: Stop
1: Operate
I2TB0
I2TB1
R/W
R/W
3
3
0
0
TMRB0
prescaler
0: Stop and clear
1: Run (Count up)
TMRB1
prescaler
0: Stop and clear
1: Run (Count up)
TB0PRUN
TB1PRUN
R/W
R/W
2
2
0
0
1
1
TMP92CF26A
2009-06-25
Up counter
(UC10)
Up counter
(UC12)
TB1RUN
TB0RUN
R/W
R/W
0
0
0
0

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