TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 330

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: The parity error flag is cleared every time it is read. However, if a parity error is detected w¥twice in succession
Note: In 9-Bit and 8-Bit + Parity Modes, interrupts coincide with the ninth bit pulse.
(13) Timing generation
and the parity error flag is read between the two parity errors, it may seem as if the flag had not been cleared.
To avoid this situation, a read of the parity error flag should be riggered by a receive interrupt.
Thus, when servicing the interrupt, it is necessary to wait for a 1-bit period (to allow the stop bit to be
transferred) to allow checking for a framing error.
2.
3.
a.
Receiving
Transmitting
b.
Interrupt timing
Framing error timing
Parity error timing
Overrun error timing
Interrupt timing
Transmission
Interrupt
timing
Receiving
Interrupt
timing
compared with the parity bit received via the RXD pin. If they are not equal, a
parity error is generated.
the majority of the samples are 0, a Framing error is generated.
Parity error <PERR>
Framing error <FERR>
In UART Mode
I/O interface
The parity generated for the data shifted into receiving buffer 2 (SC0BUF) is
The stop bit for the received data is sampled three times around the center. If
Mode
Mode
SCLK Output Mode
SCLK Input Mode
SCLK Output Mode
SCLK Input Mode
(bit 8)
Center of stop bit
(bit 8)
Center of last bit
Center of last bit
Just before stop bit is
transmitted
(Note)
92CF26A-328
9-Bit
9-Bit
―
Immediately after last bit. (See Figure 3.14.13.)
Immediately after rise of last SCLK signal Rising Mode, or
immediately after fall in Falling Mode. (See Figure 3.14.14.)
Timing used to transfer received to data Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.15.)
Timing used to transfer received data to Receive Buffer 2 (SC0BUF)
(i.e. immediately after last SCLK). (See Figure 3.14.16.)
Center of last bit
(parity bit)
Center of stop bit
Center of last bit
(parity bit)
Center of last bit
(parity bit)
Just before stop bit is
transmitted
8-Bit + Parity
8-Bit + Parity
(Note)
Center of stop bit
Center of stop bit
Center of stop bit
Center of stop bit
Just before stop bit is
transmitted
8-Bit, 7-Bit + Parity, 7-Bit
8-Bit, 7-Bit + Parity, 7-Bit
TMP92CF26A
2009-06-25