TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 333

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

BR0CR
(1203H)
BR0ADD
(1204H)
0
1
+(16−K)/16 division enable
Bit symbol
Read/Write
Reset State
Function
bit Symbol
Read/Write
Reset State
Function
BR0ADD
<BR0K3:0>
Disable
Enable
Note1:Availability of +(16-K)/16 division function
Note2:Set BR0CR <BR0ADDE> to 1 after setting K (K = 1 to 15) to BR0ADD<BR0K3:0> when +(16-K)/16 division
1111(K = 15)
0001(K = 1)
0000
The baud rate generator can be set to “1” in UART mode only when the +(16-K)/16 division function is not
used.Do not use in I/O interface mode.
Figure 3.14.8 Baud rate generator control (channel 0, BR0CR, BR0ADD)
function is used. If the unused bits in the BR0ADD register is written, it does not iaffect o operation. If that bits
is read, it becomes undefined.
to
BR0CR
<BR0S3:0>
Always
write “0”
Sets baud rate generator frequency divisor
2 to 15
1 , 16
7
0
7
−
N
0000(N = 16)
0001 (N = 1)
+(16−K)/16
division
0: Disable
1: Enable
BR0ADDE
BR0CR<BR0ADDE> = 1
Disable
Disable
UART mode
or
6
0
6
○
×
00: φT0
01: φT2
10: φT8
11: φT32
00
01
10
11
BR0CK1
Setting the input clock of baud rate generator
1111 (N = 15)
N + (16-K) /16
0010 (N = 2)
Divided by
5
5
0
Disable
to
92CF26A-331
Internal clock φT0
Internal clock φT2
Internal clock φT8
Internal clock φT32
I/O mode
BR0CK0
4
4
0
×
×
BR0CR<BR0ADDE> = 0
0001 (N = 1) (UART only)
R/W
1111(N = 15)
0000(N = 16)
Divided by N
to
BR0S3
BR0K3
3
0
3
0
(divided by N + (16-K) / 16)
Divided frequency setting
Sets frequency divisor “K”
BR0S2
BR0K2
2
0
2
0
R/W
BR0S1
BR0K1
1
0
1
0
TMP92CF26A
BR0S0
BR0K0
0
0
0
2009-06-25
0