TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 340

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note: The TXD pin of each slave controller must be in Open-Drain Output Mode.
(4) Mode 3 (9-Bit UART Mode)
parity bit cannot be added.
In the case of transmission the MSB (9th bit) is written to SC0MOD0<TB8>. In the
case of receiving it is stored in SC0CR<RB8>. When the buffer is written or read,
<TB8> or <RB8> is read or written first, before the rest of the SC0BUF data.
SC0MOD0<WU> to 1. The interrupt INTRX0 can only be generated when<RB8> = 1.
9-Bit UART Mode is selected by setting SC0MOD0<SM1:0> to 11. In this mode a
Wake-up function
In 9-Bit UART Mode, the wake-up function for slave controllers is enabled by setting
TXD
X: Don't care, −: No change
Main routine
P9CR
P9FC
SC0MOD0
SC0CR
BR0CR
INTES0
Interrupt routine
A
if A
A
CC
CC
Master
CC
≠ 0 then ERROR
Figure 3.14.17 Serial Link using Wake-up function
RXD
← X
← −
← −
← −
← 0
← X
← SC0CR AND 00011100
← SC0BUF
7
6
X
−
−
0
0
1
TXD
5
X
X
1
1
0
0
92CF26A-338
Slave1
4
X
X
−
−
1
0
3
X
X
1
−
1
X
RXD
2
−
−
0
−
0
0
1
0
X
0
−
0
0
0
−
−
1
−
0
0
TXD
Slave 2
Set P91 to function as the RXD0 pin.
Enable receiving in 8-bit UART mode.
Add odd parity.
Set the transfer rate to 9600 bps.
Enable the INTTX0 interrupt and set it to interrupt
level 4.
Check for errors
Read the received data
RXD
TXD
Slave 3
TMP92CF26A
RXD
2009-06-25