TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 348

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.15.2
3.15.3
S
S
S
Slave address
Slave address
(a) Addressing format
(b) Addressing format (with restart)
(c) Free data format (data transferred from master device to slave device)
operation status.
Serial Bus Interface (SBI) Control
The Data Formats in the I
8 bits
Data
The following registers are used to control the serial bus interface and monitor the
The data formats in the I
8 bits
8 bits
• Serial bus interface control register 0 (SBICR0)
• Serial bus interface control register 1 (SBICR1)
• Serial bus interface control register 2 (SBICR2)
• Serial bus interface data buffer register (SBIDBR)
• I
• Serial bus interface status register (SBISR)
• Serial bus interface baud rate register 0 (SBIBR0)
1
S:
1
1
2
Start condition
R/
ACK:
P: Stop condition
C bus address register (I2CAR)
W
W
R
W
R
:
/
/
C
A
K
1
A
C
K
1
C
1
A
K
Figure 3.15.2 Data format in the I
Direction bit
Acknowledge bit
1 to 8 bits
1 to 8 bits
1 to 8 bits
Data
1 or more
Data
Data
2
2
C Bus Mode
C bus mode is shown below.
92CF26A-346
1 or more
1 or more
A
C
K
1
A
C
K
1
A
C
K
1
S
1 to 8 bits
1 to 8 bits
Slave address
Data
Data
2
C bus mode
8 bits
1
C
1
A
K
C
1
A
K
W
R
P
/
P
A
C
K
1
1 to 8 bits
1 or more
Data
TMP92CF26A
2009-06-25
C
1
A
K
P