TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 350

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SBICR1
(1240H)
A read-
modify-write
operation
cannot be
performed
Bit symbol
Read/Write
Reset State
Function
Note1: For the frequency of the SCL line clock, see 3.15.5 (3) Serial clock.
Note2: The initial data of SCK0 is “0”, the initialdata of SWRMON is “1” if SBI operation is enable (SBICR0<SBIEN>
Note3: This I
= “1”). If SBI operation is disable (SBICR0<SBIEN> = “0”), the initialdata of SWRMON is “0”.
circuit itself allows the setting of a baud rate over 100kbps, the compliance with the I
guaranteed in that case.
2
C bus circuit does not support Fast-mode, it supports the Standard mode only. Although the I
BC2
7
Number of transferred bits
0
Figure 3.15.4 Registers for the I
(Note 1)
R/W
BC1
Serial Bus Interface Control Register 1
6
0
BC0
5
0
92CF26A-348
Acknowledge
mode
specification
0: Not
1:Generate
generate
ACK
R/W
4
0
Software reset state monitor <SWRMON> at read
Number of bits transferred
Internal serial clock selection <SCK2:0> at write
f
Acknowledge mode specification
<BC2:0>
SYS
000
001
010
011
100
101
110
111
0
1
0
1
000
001
010
011
100
101
110
111
=80MHz (Output to SCL pin), Clock gear = fc/1
Always
read as
“1”.
(Reserved)
During software reset
(Initial Data)
Not generate clock pulse for acknowledge signal
Generate clock pulse for acknowledge signal
2
C bus mode
n = 10
n = 4
n = 5
n = 6
n = 7
n = 8
n = 9
3
R
−
1
clock pulses
Number of
8
1
2
3
4
5
6
7
<ACK> = 0
(Reserved)
19 kHz
−(Note3)
−(Note3)
−(Note3)
−(Note3)
68 kHz
36 kHz
Internal serial clock selection and
SCK2
2
0
software reset monitor
Bits
R/W
8
1
2
3
4
5
6
7
System Clock: f
Clock Gear : fc/1
fscl =
SCK1
1
0
clock pulses
Number of
2
C specification is not
2
f
SYS
n
9
2
3
4
5
6
7
8
+ 36
<ACK> = 1
TMP92CF26A
SWRMON
0/1
/4
SCK0/
R/W
(Note2)
0
2009-06-25
SYS
[Hz]
(=80MHz)
2
C bus
Bits
8
1
2
3
4
5
6
7