TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 355

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Internal SCL output
(Master A)
Internal SCL output
(Master B)
SCL pin
(4)
(5)
b.
and <ALS> to the I2CAR. Clear the <ALS> to “0” for the address recognition mode.
Clear the SBICR2<MST> to “0” for operation as a slave device. The <MST> is cleared
to “0” by the hardware after a stop condition on the bus is detected or arbitration is
lost.
Slave address and address recognition mode specification
Master/Slave selection
When the TMP92CF26A is used as a slave device, set the slave address <SA6:0>
Set the SBICR2<MST> to “1” for operating the TMP92CF26A as a master device.
down a clock line to low-level, in the first place, invalidate a clock pulse of another
master device which generates a high-level clock pulse. The master device with a
high-level clock pulse needs to detect the situation and implement the following
procedure.
The TMP92CF26A has a clock synchronization function for normal data transfer
even when more than one master exists on the bus.
The example explains the clock synchronization procedures when two masters
simultaneously exist on a bus.
the SCL line of the bus becomes the Low-level. After detecting this situation,
Master B resets a counter of High-level width of an own clock pulse and sets the
internal SCL output to the Low-level.
Master A finishes counting Low-level width of an own clock pulse at point “b” and
sets the internal SCL output to the High-level. Since Master B holds the SCL line
of the bus at the Low-level, Master A wait for counting high-level width of an own
clock pulse. After Master B finishes counting low-level width of an own clock pulse
at point “c” and Master A detects the SCL line of the bus at the High-level, and
starts counting High-level of an own clock pulse. The clock pulse on the bus is
determined by the master device with the shortest High-level width and the
master device with the longest Low-level width from among those master devices
connected to the bus.
Clock synchronization
In the I
As Master A pulls down the internal SCL output to the Low level at point “a”,
2
C bus mode, in order to wired-AND a bus, a master device which pulls
Figure 3.15.9 Clock synchronization
a
Reset a counting of
high-level width of a
clock pulse
92CF26A-353
Wait counting high-level
width of a clock pulse
b
c
Start counting high-level width of a clock pulse
TMP92CF26A
2009-06-25