TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 36

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Block
SYSCR2 <HALTM1:0>
•
•
CPU, MAC
I/O ports
TMRA, TMRB
SIO,SBI
A/D converter
WDT
I2S, LCDC, SDRAMC,
Interrupt controller,
SPIC, DMAC, NDFC,
USB
RTC, MLD
(2) How to release the Halt mode
HALT Mode
Release by interrupt requesting
Release by resetting
release sources are determined by the combination of the states of the interrupt mask
register <IFF2:0> and the halt modes. The details for releasing the HALT status are
shown in Table 3.3.5.
When the interrupt request level set before executing the HALT instruction exceeds
the value of the interrupt mask register, the interrupt is processed depending on its
status after the HALT mode is released, and the CPU status executing the instruction
that follows the HALT instruction. When the interrupt request level set before
executing the HALT instruction is less than the value of the interrupt mask register,
HALT mode release is not executed.(in non-maskable interrupts, interrupt processing
is processed after releasing the halt mode regardless of the value of the mask register.)
However
INTKEY,INTRTC, INTALM interrupts, even if the interrupt request level set before
executing the HALT instruction is less than the value of the interrupt mask register,
HALT mode release is executed. In this case, the interrupt is processed, and the CPU
starts executing the instruction following the HALT instruction, but the interrupt
request flag is held at “1”.
resetting time for operation of the oscillator to stabilize.
before the “HALT” instruction is executed. However the other settings contents are
initialized. (Releasing due to interrupts keeps the state before the “HALT” instruction
is executed.)
The operation of each of the different Halt Modes is described in Table 3.3.4.
These HALT states can be released by resetting or requesting an interrupt. The halt
The HALT mode release method depends on the status of the enabled interrupt.
Release of all halt statuses is executed by resetting.
When the STOP mode is released by RESET, it is necessary to allow enough
When releasing the halt mode by resetting, the internal RAM data keeps the state
only
Table 3.3.4 I/O operation during Halt Modes
for
INT0
Available to select
Operation block
92CF26A-34
Operate
IDLE2
11
to
Depends on PxDR register setting
INT5,
INT6,
Stop
Operate
INT7(unsynchronous
IDLE1
10
Stop
STOP
TMP92CF26A
01
2009-06-25
interrupt),