TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 360

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.15.6
(1) Device initialization
(2) Start condition and slave address generation
Data Transfer in I
Setting in main routine
In INTSBI interrupt routine
SBICR1 to “0”.
Set a slave address <SA6:0> and the <ALS> (<ALS> = “0” when an addressing format)
to the I2CAR.
For specifying the default setting to a slave receiver mode, clear “0” to the <MST, TRX,
BB> and set “1” to the <PIN>, “10” to the <SBIM1:0>.
SBICR1 ← 0 0 0 X 0 X X X
I2CAR
SBICR2 ← 0 0 0 1 1 0 0 0
Note: X: Don’t care
Reg.
Reg.
if Reg.
Then
SBICR1
SBIDBR1 ← X X X X X X X X
SBICR2
Set the SBICR1<ACK, SCK2:0>, Set SBIBR1 to “1” and clear bits 7 to 5 and 3 in the
follows.
Check a bus free status (when <BB> = “0”).
Set the SBICR1<ACK> to “1” (Acknowledge Mode) and specify a slave address
and a direction bit to be transmitted to the SBIDBR.
When SBICR2<BB> = “0”, the start condition are generated by writing “1111” to
SBICR2<MST, TRX, BB, PIN>. Subsequently to the start condition, nine clocks
are output from the SCL pin. While eight clocks are output, the slave address and
the direction bit which are set to the SBIDBR. At the 9th clock, the SDA line is
released and the acknowledge signal is received from the slave device.
An INTSBI interrupt request occurs at the falling edge of the 9th clock. The
<PIN> is cleared to “0”. In the Master Mode, the SCL pin is pulled down to the
Low-level while <PIN> is “0”. When an interrupt request occurs, the <TRX> is
changed according to the direction bit only when an acknowledge signal is
returned from the slave device.
a.
In the Master Mode, the start condition and the slave address are generated as
INTCLR ← 0X2a
Process
End of interrupt
← X X X X X X X X
Master Mode
← SBISR
← Reg. e 0x20
← X X X 1 X X X X
← 1 1 1 1 1 0 0 0
≠ 0x00
7 6 5 4 3 2 1 0
7 6 5 4 3 2 1 0
2
C Bus Mode
Clear the interrupt request
92CF26A-358
Set acknowledge and SCL clock.
Set slave address and address recognition mode.
Set to slave receiver mode.
Wait until bus is free.
Set to acknowledgement mode.
Set slave address and direction bit.
Generate start condition.
TMP92CF26A
2009-06-25