TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 363

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

interrupt request
interrupt request
SDA pin
SCL pin
SDA pin
SCL pin
INTSBI
<PIN>
INTSBI
<PIN>
Figure 3.15.16 Example of when <BC2:0> = “000”, <ACK> = “1” in receiver mode
Figure 3.15.17 Termination of data transfer in master receiver mode
When the <TRX> is “0” (Receiver mode)
Read SBIDBR
D7
“0” → <ACK>
Read SBIDBR
read the received data from SBIDBR to release the SCL line (data which is read
immediately after a slave address is sent is undefined). After the data is read,
<PIN> becomes “1”.
outputs “L” level from SDA pin with acknowledge timing.
TMP92CF26A pulls down the SCL pin to the Low-level. The TMP92CF26A
outputs a clock pulse for 1-word of data transfer and the acknowledge signal each
time that received data is read from the SBIDBR.
“0” before reading data which is 1-word before the last data to be received. The
last data word does not generate a clock pulse as the Acknowledge signal. After
the data has been transmitted and an interrupt request has been generated, set
<BC2:0> to “001” and read the data. The TMP92CF26A generates a clock pulse for
a 1-bit data transfer. Since the master device is a receiver, the SDA line on the bus
remains High. The transmitter interprets the High signal as an ACK signal. The
receiver indicates to the transmitter that data transfer is complete.
After the one data bit has been received and an interrupt request been generated,
the TMP92CF26A generates a stop condition (see Section 3.15.6 (4) Stop condition
generation) and terminates data transfer.
D7
1
1
When the next transmitted data is other than 8 bits, set <BC2:0> <ACK> and
Serial clock pulse for transferring new 1 word of data is defined SCL and
An INTSBI interrupt request then occurs and the <PIN> becomes “0”, Then the
In order to terminate the transmission of data to a transmitter, clear <ACK> to
D6
D6
2
2
D5
D5
3
3
92CF26A-361
D4
D4
4
4
D3
D3
5
5
D2
D2
6
6
D1
D1
7
7
D0
D0
8
8
Output from Master
Output from Slave
ACK
Output of Master
Output of Slave
9
1
“001” → <BC2:0>
Read SBIDBR
TMP92CF26A
Acknowledge signal
sent to a transmitter
Acknowledge signal
to a transmitter
New D7
2009-06-25