TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 365

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

SBICR1
SBIDBR
Note: X: Don’t care
Example: In case matching slave address in slave receive mode, direction bit is “1”.
INTSBI interrupt
if TRX = 0
Then shift to other process
if AL = 1
Then shift to other process
if AAS = 0
Then shift to other process
slave mode after losing arbitration.
receives a slave address or a GENERAL CALL from the master device, or when a
GENERAL CALL is received and data transfer is complete, or after matching
received address. In the master mode, the TMP92CF26A operates in a slave mode
if it losing arbitration. An INTSBI interrupt request occurs when a word data
transfer terminates after losing arbitration. When an INTSBI interrupt request
occurs the <PIN> is cleared to “0” and the SCL pin is pulled down to the Low-level.
Either reading/writing from/to the SBIDBR or setting the <PIN> to “1” will
release the SCL pin after taking tLOW time.
Check the SBISR<AL>, <TRX>, <AAS>, and <AD0> and implements processes
according to conditions listed in the next table.
b.
In the slave mode the TMP92CF26A operates either in normal slave mode or in
In the slave mode, an INTSBI interrupt request occurs when the TMP92CF26A
If <MST> = 0 (Slave Mode)
← X X X 1 X X X X
← X X X X X X X X
7 6 5 4 3 2 1 0
92CF26A-363
Set the bit number of transmit.
Set the data of transmit.
TMP92CF26A
2009-06-25