TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 367

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(4) Stop condition generation
writing “1” to SBICR2<MST, TRX, PIN> and “0” to SBICR2<BB>. Do not modify the
contents of SBICR2<MST, TRX, PIN, BB> until a stop condition has been generated
on the bus. When the bus’s SCL line has been pulled Low by another device, the
TMP92CF26A generates a stop condition when the other device has released the SCL
line and SDA pin rising.
“1” → <MST>
“1” → <TRX>
“0” → <BB>
“1” → <PIN>
Internal SCL
SCL Pin
SDA Pin
<PIN>
<BB> (Read)
SBICR2 ← 1 1 0 1 1 0 0 0
When SBISR<BB> = “1”, the sequence for generating a stop condition start by
“1” → <MST>
“1” → <TRX>
“0” → <BB>
“1” → <PIN>
Internal SCL
SCL pin
SDA Pin
<PIN>
<BB> (Read)
Figure 3.15.18 Stop condition generation (Single master)
Figure 3.15.19 Stop condition generation (Multi master)
7 6 5 4 3 2 1 0
92CF26A-365
The case of pulled low
by another device
Generate stop condition.
Stop condition
Stop condition
TMP92CF26A
2009-06-25