TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 373

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

3.16.2
3.16.2.1 SFRs
• INTUSB (interrupt from UDC) generation
• A bridge for SFR
• USB clock control (48 MHz)
functions are as follow.
900/H1 CPU I/F
The 900/H1 CPU I/F is a bridge between the 900/H1 CPU and the UDC. Its main
transceiver.
The 900/H1 CPU I/F incorporates the following SFRs to control the UDC and USB
• USB control
• USB interrupt control
USBCR1
USBINTFR1
USBINTFR2
USBINTFR3
USBINTFR4
USBINTMR1
USBINTMR2
USBINTMR3
USBINTMR4
Address
07F0H
07F1H
07F2H
07F3H
07F4H
07F5H
07F6H
07F7H
07F8H
Table 3.16.1 900/H1 CPU I/F SFR
Read/Write
92CF26A-371
(USB control register 1)
(USB interrupt flag register 1)
(USB interrupt flag register 2)
(USB interrupt flag register 3)
(USB interrupt flag register 4)
(USB interrupt mask register 1)
(USB interrupt mask register 2)
(USB interrupt mask register 3)
(USB interrupt mask register 4)
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SFR Symbol
USBINTMR1
USBINTMR2
USBINTMR3
USBINTMR4
USBINTFR1
USBINTFR2
USBINTFR3
USBINTFR4
USBCR1
TMP92CF26A
2009-06-25