TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 393

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Note1: In receive mode, if the endpoint bits corresponding to packet-A or paclet-B are “1”, read the required
Note2: In transmit mode, if both A and B bits are not “1”, this means there is space in FIFO. So, write data of payload
Note3: In dual packet transmit mode, if both A and B packet are empty and EOP<EPn_EOPB> is written “0”, the
Note4:No data is set in this register when NULL-packet (0Length-packet) is received
packet-number data after checking EPx_SIZE<PKT_ACTIVE>.
or less to FIFO. If the transmission is short-packet, write “0” to EOP<EPn_EOPB> after writing data to the FIFO.
The maximum size that can be written to A or B packet is the same as the maximum payload size. If both A and
B bits are “0”, continuous writing of double maximum payload size is available.
NULL-data is set to FIFO. In single mode, the NULL-data is also set to FIFO if the above operation is executed
when packet-A contains no data.
92CF26A-391
TMP92CF26A
2009-06-25