TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 396

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

FIFO_DISABLE (Bit1)
STAGE_ERROR (Bit0)
0: FIFO enabled
1: FIFO disabled
0: SUCCESS
1: ERROR
When this bit is “1”, this bit is cleared to “0” by read
EP0_STATUS register. This bit is not cleared even if normal
control transfer or other transfer is executed after. To clear, read
this bit. When software transaction is finished and UDC writes
EOP register, UDC shifts to status register and
termination of status stage. In this case, if software is needed to
confirm that the status stage has been terminated correctly, when
a new request flag is received, it is possible to confirm whether or
not the last request has been terminated correctly. It can also be
confirmed, when a new request flag is asserted, whether or not
the last request has been cancelled before completion.
handshake for all transfers. Disabled or enabled status is set the
COMMAND register. This bit is cleared to “0” when transfer type
is changed.
terminated correctly. ERROR is set when a status stage is not
terminated correctly and a new SETUP token is received.
This bit symbol shows FIFO status except for EP0.
If the FIFO is set to disabled, the UDC transmits NAK
This bit symbol shows that the status stage has not been
92CF26A-394
TMP92CF26A
2009-06-25
waits