TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 4

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(10) USB (universal serial bus) controller: 1 channel
(11) I
(12) LCD controller
(13) SDRAM controller:1 channel
(14) Timer for real-time clock (RTC)
(15) Key-on wakeup (Interrupt key input)
(16) 10-bit A/D converter (Built in Sample Hold circuit): 6 channels
(17) Touch screen interface
(18) Watchdog timer
(19) Melody/alarm generator
(20) MMU
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2
S (Inter-IC Sound)interface: 2 channels
Endpoint 1: BULK (output) 64 bytes × 2 FIFOs
Endpoint 2: BULK (input) 64 bytes × 2 FIFOs
Endpoint 3: Interrupt (input) 8 bytes × 1 FIFO
Supports USB (ver.1.1)
Full-speed (12 Mbps) (Low-speed is not supported.)
Endpoint 0: Control 64 bytes × 1 FIFO
Descriptor RAM: 384 bytes
I
Data Format is supported Left/Right Justify
128-byte FIFO buffer (64 bytes × 2) per channel
Supports monochrome, 4, 16 and 64 gray levels and 256/4096/65536 colors for STN
Supports 4096/65536/262144/16777216 colors for TFT
Supports PIP (Picture In Picture Display)
Supports H/W Rotation function for support to various LCDM
Supports 16-Mbit, 64-Mbit, 128-Mbit, 256-Mbit and 512-Mbit SDR (Single-data-rate)
Possible to execute instruction on SDRAM
Based on TC8521A
Built-in Switch of Low-resistor, and available to reduce external components for shift
Melody: Output of a clock 4 to 5461-Hz clock
Alarm: Output of 8 kinds of alarm pattern
5 kinds of interval interrupt
Expandable up to 3.1 Gbytes (3 local area/8 bank method)
Independent bank for each program, read data, write data, source and destination of
SDRAM
change row/column
DMAC (Odd channel/Even channel) and LCD display data
2
S bus mode selectable (Master, transmission only)
92CF26A-2
TMP92CF26A
2009-06-25