TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 407

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

USB STATE
(07CEH)
INT_Control
(07D6H)
bit Symbol
Read/Write
Reset State
bit Symbol
Read/Write
Reset State
3.16.3.22 INT_Control Register
3.16.3.23 USB STATE Register
Note: When writing to this register, a recovery time of 5clocks at 12MHz is needed. After writing this register, insert
dummy instruction of 420 ns or longer.
register.
becomes disabled.
(smaller than the data length that is specified by the host as wLength), the device side
and stage management cannot be synchronized. Therefore, INT_STASN interrupt
signals this shift to status stage. If needed, set to “1” after receiving setup packet.
these bits (Configured, Addressed and Default). If transaction for SET_CONFIG
request is executed by using software, write the present state to this register. If host
appointconfig is 0, this becomes Unconfigured, and it is necessary to return to
Addressed state. Therefore, if host appoint config is 0, write “0” to bit2.
by hardware. When host appoint config value that supported by device, device must
execute mode setting for each endpoint by using the value that is appointed by
endpoint-descriptor in the config-descriptor. After finish mode setting, set Configured
bit (Bit2) to “1” before accessing EOP register. When this bit is set to “1”, Addressed bit
(Bit1) is set to “0” automatically.
INT_STASN interrupt is disabled and enabled by the value that is written to this
This is initialized to disable by external reset. When setup packet is received, it
In control read transfer, if the host terminates a dataphase with small data length
This register shows the current device state for connection with USB host.
Inside the UDC, the answer for each Device Request is managed by referring to
When Configured bit (Bit2) is written “0”, Addressed bit (bit 1) is set automatically
STATUS_NAK (Bit0)
Bit2 to bit0
7
7
0: INT_STATSN interrupt disable
1: INT_STATSN interrupt enable
000: Default
010: Addressed
100: Configured
6
6
92CF26A-405
5
5
4
4
3
3
Configured
R/W
2
2
0
Addressed
1
1
R
0
TMP92CF26A
2009-06-25
Status_nak
Default
R/W
R
0
0
0
1