TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 422

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

There is no dataphase
There is dataphase
bmRequestType
bmRequestType
010000xxB
010000xxB
(b) Control write/request
bRequest, wValue, wIndex, wLength registers and process each request.
According to application, access Setup_Received register after request has been
identified. UDC must also be informed that the INT_SETUP interrupt has been
recognized. If application processing is finished, write “0” to EP0 bit of EOP
register. When UDC receives this, the status stage finish automatically.
bmRequestType, bRequest, wValue, wIndex, wLength registers and process each
request. According to application, access Setup_Received register after request
has been identified. UDC must also be informed that the INT_SETUP interrupt
has been recognized.
confirm EP0_DSET is “1”. After confirming, read data FIFO of endpoint 0. If
receiving data is more than payload, write data after it confirming whether the
EP0_DSET_A bit in DATASET register is “1”. (INT_ENDPOINT0 interrupt can be
used.) If reading all data is finished, write “0” to EP0 bit of EOP register. When
UDC receives this, the status stage finishes automatically.
finishing status stage normally is recognized by external application, manage this
stage by using this interrupt signal. If status stage cannot be finished normally
and during status stage, a new SETUP token may be received. In this case, when
INT_SETUP interrupt signal is asserted, “1” is set to STAGE_ERROR bit of
EP0_STATUS register informing externally that the status stage cannot be
finished normally.
When INT_SETUP is received, identify contents of request by bmRequestType,
When INT_SETUP is received, identify contents of device request by
After receiving data prepared in application, access DATASET register, and
INT_STATUS interrupt is asserted when UDC finishes status stage normally. If
Vendor specific
Vendor specific
bRequest
bRequest
Vendor specific
Vendor specific
92CF26A-420
wValue
wValue
Vendor specific
Vendor specific
wIndex
wIndex
Vendor specific
(Except for 0)
wLength
wLength
0
TMP92CF26A
Vendor data
2009-06-25
Data
None
Data