TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 423

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

Start up
EP0 bit = 1
Enumeration
WR number of payload
to EP0_FIFO register
Total = Total − payload
DATASET
Note : This chart does not cover special cases in this flow such as overlap receive SETUP packet.
register
Check
Total ≥ payload
Abnormal
Normal
Please refer to 3.16.6 (2) (c) Control transfer type.
finish
finish
Get_Vendor_Request
Control RD transfer
in Set_Config (Interface)
EP0 bit = 0
Setting each EP mode
Figure 3.16.2 Control Flow in UDC as seen from Application
process
Below is control flow in UDC as seen from application.
Receive
except
INT_STATUS
Receive
INT_STAS
Total_Length calculation
WR number of rest data
to EP0_FIFO
Total = 0
process in UDC
Transmit
Status finish
Total < payload
Access to SetupReceived register
92CF26A-421
Identify request RD
IDLE
WR “0” only EP0 bit0 of
RD number of payload
from EP0_FIFO register
Total = Total − payload
EP0 bit = 0
Total > payload
EOP register
DATASET
register
Check
EP0 bit = 1
Standard request
Printerclass request
RD number of rest data
from EP0_FIFO
Total = 0
Control WR transfer
Set_Vendor_Request
Total ≤ payload
process
Total_Length calculation
Receive
TMP92CF26A
2009-06-25
processed
Total = 0
Total = 0
Not