TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 434

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(c-2) Data stage
(c-3) Status stage
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transaction except for the following differences;
IN or OUT token. It uses a transaction in the opposite direction to the preceding
stage.
point, CPU must write “0” to EP0 bit of EOP register in last transaction for status
stage to finish normally.
Data stage is configured by one or several transactions based on toggle sequence.
The transaction is the same as for format transmission or receiving bulk
Status stage is configured 0-data-length packet with DATA1’s PID and handshake
The combination is given below.
UDC processes status stage base of control flow in control transfer type. At this
Details of status stage are given below.
(c-3-1) IN status stage
1.
2.
3.
Toggle bit starts from “1” by SETUP stage.
It determines whether right or not by comparing IN and OUT token with direction
bit of device request. If a token of the opposite direction is received, it is recognized
as status stage.
INT_ENDPOINT0 interrupt is asserted.
Control read transfer type: OUT
Control write transfer type: IN
Control write transfer type (not dataphase): IN
• Token: IN
• Data: DATA1 (0 data length), NAK, STALL
• Handshake: ACK
• INVALID condition: State returns to IDLE.
• STALL condition: Stall handshake is returned and state returns to IDLE.
Confirmation of whether EOP register is accessed or not is carried out externally.
If it is not accessing, NAK handshake is returned to continue control transfer
and state returns to IDLE.
IN status stage transaction format is given below.
Control flow
The transaction flow of IN status stage in UDC is given below.
Token packet is received and address, endpoint number and error are
confirmed. If it does not correspond, the state returns to IDLE. If status stage
is enabled based on stage control flow in the UDC, advance to next stage.
STATUS register state is confirmed.
If EOP register is access is confirmed, 0-data-length data packet and CRC are
transmitted.
92CF26A-432
TMP92CF26A
2009-06-25