TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 435

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

4.
(c-3-2) OUT status stage
1.
2.
3.
4.
normally, the UDC sets error to STATUS register.
normally, the UDC sets error to STATUS register. For sequence of this protocol,
refer to section supplement.
• Set STATU to READY.
• Assert INT_STATUS interrupt.
• Set STATUS register to TX_ERR and state returns to IDLE and wait for
• Token: OUT
• Data: DATA1 (0 data length)
• Handshake: ACK, NAK, STALL
• INVALID condition: State returns to IDLE.
• STALL condition: Data is cleared, stall handshake is returned, and state
Whether EOP register is accessed or not is confirmed externally. If it is not
accessed, NAK handshake is returned to continue control transfer and state
returns to IDLE.
• Set STATUS to READY.
• Assert INT_STATUS interrupt.
• Set RX_ERR to STATUS register and return to IDLE. It waits to retry status
It finishes normally by the above transaction.
If a time out occurs without receiving ACK from host,
At this point, if new SETUP stage is started without status stage finishing
The transaction format for OUT status stage is given below.
Control flow
The transaction flow for OUT status stage in the UDC is given below.
It finishes normally by the above transaction.
If there is an error in data, ACK handshake is not returned.
At this point, if new SETUP stage is started without status stage finishing
If ACK handshake from host is received,
Token packet is received and address, endpoint number and error are
confirmed. If they do not correspond, the state returns to IDLE. If status stage
is enabled base on stage control flow in the UDC, advance to next stage.
STATUS register state is confirmed.
If EOP register is access is confirmed, 0-data-length data packet and CRC are
received.
If there is no error in data, ACK handshake is transmitted to host.
restring status stage.
stage.
92CF26A-433
returns to IDLE.
TMP92CF26A
2009-06-25