TMP92xy26AXBG Toshiba, TMP92xy26AXBG Datasheet - Page 436

• Manufacturer Part Number: TMP92xy26AXBG
• Manufacturer: Toshiba

Specifications of TMP92xy26AXBG

• Package: FPGA228
• Rom Types(m=mask,p=otp, F=flash,e=eeprom): Romless
• Rom Combinations: Romless
• Ram Combinations: 144/288
• Architecture: 32-bit CISC
• Usb/spi Channels: 1/1
• Uart/sio Channels: 2
• I2c/sio Bus Channels: 1
• (s)dram Controller: 1
• Adc 10-bit Channel: 6
• Da Converter: -
• Timer 8-bit Channel: 8
• Timer 16-bit Channel: 2
• Pwm 8-bit Channels: -
• Pwm 16-bit Channels: -
• Cs/wait Controller: 4
• Dual Clock: Y
• Number Of I/o Ports: 136
• Power Supply Voltage(v): 3.0 to 3.6

(c-4) Stage management
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Each stage in control transfer type has to process combination software. UDC detects
the following contents from 8-byte data in SETUP stage. The stage is managed by
determining control transfer type.
transfer type, or control write transfer type (No data stage).
of internal UDC, NAK handshake is returned and BUSY is informed to USB host. In
all control transfer types, if SETUP token is received from host current transaction is
stopped, and it switches to SETUP stage in the UDC. The CPU receives new
INT_SETUP even if it is processing previous control transfer.
The UDC manages each stage of control transfer by hardware.
Each stage is changed by receiving token from USB host, or CPU accesses register.
Based on these it is determines to be either control read transfer type control write
Various conditions for changing stage in control transfer are given below.
If receiving token for next stage from host before switching to next stage from state
Whether there is data stage or not
Data stage direction
92CF26A-434
TMP92CF26A
2009-06-25